CTS (clock tree synthesis)

CLOCK TREE SYNTHESIS

 

Pre checks for CTS

1)     The clock sources and generated clocks should be defined in constraints

2)     The block should be placed and optimized with out legalization errors,                    

 check_legality  -verbose can be used

3)     The blocks estimated QOR should be as per requirements like congestion free, Timing, Max cap, Max tran

4)     Active scenarions are defined

5)     Vdd and Vss power nets are pre routed

6)     High fanout nets such as scan enable are synthesized with buffers

Defining the Clock Trees

               The tool derives the clock trees based on clocks defined in constraints of the block, If the derived clock do not meet the requirements the we can define the clock clock tree with defining clock tree exceptions which are derived from clock tree exception from ideal clock latencies and handling endpoints with balancing conflicts.

 

The tool derives the clock tree by tracing through the transitive fanout from clock root to clock endpoints. In general tracing terminates when finds a clock pin of a sequential cell or macro , but the clock traces through sequential cells if they are ICG cells or their fanout drives a generated clock.

If Xor or Xnor are used as ICG , Which are non unate . ie  the tool uses both positive and negative unate timing arcs for tracing clock path, if this do not correspond to functional mode of block then we use  set_case_analysis command to hold all nonclock inputs of cell at constant value by which the cell forces into functional mode for clock tree synthesis.

Clock defining

Create_clock  or create_generated_clock

Check_clock_trees  command used to verify the master sources are correctly defined

 

If block containing generated clocks ensure that master clock sources are correctly defined as incorrect definitions can result in poor skew and timing QoR, and even it can not balance the sink pins of the generated clock with sink pins of its source, The tool even cannot synthesis a clock tree for generated clock to its source.

 

Set_driving_cell -lib_cell mylib/CLKBUF [get_ports CLK1]

If the clock root is an input port without an I/O pad cell. You must accurately specify the driving cell of theinput port

If you specify a week driving cell, the tool might insert extra buffers to try to meet the clock tree design rule constraints such as max transition and max capacitance, If you not specify driver cell then the tool assumes the port as infinite drive strength

If clock root is an input port with an I/O pad cell, you must accurately specify the input transition time of the input port.

set_input_transition  -rise 0.3 [get_ports CLK1]

set_input_transition  -fall 0.2  [get_ports CLK1]

 

Clock Endpoints:

Tool identifies two types of endpoints a) sink pins b) Ignore pins.

Sink pins are the clock endpoints that are used for delay balancing. Tool assigns an insertion delay of zero to all sink pins and uses this delay during delay balancing. Sink pins also referred as balancing pins.

During clock tree synthesis the tool uses sink pins in calculation and optimization for both design rule constraints and clock tree timing of skew and insertion delay

The sink pins are clock pind that drives a sequential cell , unless that cell drives a generated clock, a clock pin on a macro cell,

 

Ignore pins are clock end points that are excluded from clock tree timing calculations and optimizations. The tool uses ignore pins only in  calculations and optimizations for design rule constraints. Then endpoints of ignore pins are source pins of clock trees in the fanout of another clock.

Source pins of clock trees in the fanout of another clock

Nonclock input pins of sequential cells
• Three-state enable pins
• Output ports
• Incorrectly defined clock
• Buffer or inverter input pins that are held constant by using the set_case_analysis
command
Note:
The tool does not synthesize a clock tree if its source is held constant by
using the set_case_analysis command.
• Input pins of combinational cells or integrated clock-gating cells that do not have any
fanout or that do not have any enabled timing arcs
To verify that the tool has correctly identified the sink pins and ignore pins, examine the
clock trees in the GUI,

If the default sink and ignore pins are correct, you are done with the clock tree definition.
Otherwise, first identify any timing settings, such as disabled timing arcs and case analysis
settings, that affect the clock tree traversal. To identify disabled timing arcs in the block,
use the report_disable_timing command. To identify case analysis settings in the
block, use the report_case_analysis command. Remove any timing settings that cause
an incorrect clock tree definition.