Placement

check_legality

>>Placement and Optimization Concepts

Placement is the process of finding a suitable physical location for each cell in the block. 

Placement is performed in two stages: coarse placement and legalization.

During coarse placement, the IC Compiler II tool determines an approximate location for 

each cell according to the timing, congestion, and multi voltage constraints. The placed cells 

do not fall on the placement grid and might overlap each other. Large cells, such as RAM 

and IP blocks, act as placement blockages for smaller, leaf-level cells. Coarse placement is 

fast and is sufficiently accurate for initial timing and congestion analysis.

During legalization, the IC Compiler II tool moves the cells to legal locations on the 

placement grid and eliminates any overlap between cells. These small changes to cell 

locations cause the lengths of the wire connections to change, possibly causing new timing 

violations. Such violations can often be fixed by incremental optimization, for example, by 

resizing the driving cells

>> Placement Constraints

Placement constraints provide guidance during placement, optimization, and legalization. 

The IC Compiler II tool supports the following types of placement constraints

===>Placement Blockages

A placement blockage is an area that cells must avoid during placement, optimization, and 

legalization, including overlapping any part of the placement blockage. A placement 

blockage can be hard or soft.

>>A hard blockage prevents cells from being placed in the blockage area.

>>A soft blockage restricts the coarse placer from putting cells in the blockage area, but 

optimization and legalization can place cells in a soft blockage area.

>>If you define both hard and soft placement blockages in a block, the hard placement 

blockages take priority over the soft placement blockages in places where they overlap.

The IC Compiler II tool supports two types of placement blockages

• Keepout Margins

create_keepout_margin -outer {10 10 10 10} my_macro

create_keepout_margin -tracks_per_macro_pin 0.6 \

-min_padding_per_macro 0.1 -max_padding_per_macro 0.2 my_macro

• Area-Based Placement Blockages

create_placement_blockage -boundary {120 75 230 200} \

-type hard_macro

 create_placement_blockage -boundary {120 75 230 200} \

-type soft

create_placement_blockage -boundary {10 20 100 200} \

-type partial -blocked_percentage 40

 get_placement_blockages

 remove_placement_blockages -all

===>Placement Bounds

A placement bound is a constraint that controls the placement of groups of leaf cells and 

hierarchical cells. It allows you to group cells to minimize wire length and place the cells at 

the most appropriate locations

Soft move bound The tool tries to place the cells in the move bound within a specified 

region; however, there is no guarantee that the cells are placed inside 

the bounds.

create_bound -name name [-type soft] -boundary {coordinates}

[bound_objects]

create_bound -name b1 -boundary {100 100 200 200} INST_1

Hard move bound The tool must place the cells in the move bound within a specified 

region

create_bound -name name -type hard -boundary {coordinates}

[bound_objects]

create_bound -name b2 -type hard -boundary {100 100 200 200} INST_1

Exclusive move bound The tool must place the cells in the move bound within a specified 

region and it must place all other cells outside of the bounds.

create_bound -name name -exclusive -boundary {coordinates}

[bound_objects]

 create_bound -name b3 -exclusive -boundary {100 100 200 200} INST_1

Soft group bound The tool tries to place the cells in the group bound within a floating 

region; however, there is no guarantee that the cells are placed inside 

the bounds.

create_bound -name name [-type soft] -dimensions {width height}

[bound_objects]

 create_bound -name b4 -dimensions {100 100}  {INST_1 INST_2}

Hard group bound The tool must place the cells in the group bound within a floating 

region, whose actual coordinates are determined by the tool

create_bound -name name -type hard -dimensions {width height}

[bound_objects]

 create_bound -name b5 -type hard -dimensions {100 100} {INST_1 INST_2}

Dimensionless group bound The tool determines the shape and location of the group bound based 

on the effort used to bring cells closer inside the group bound.

create_bound -name name [-effort effort_level] [bound_objects]

The default effort is medium; you can also specify low, high, or ultra

create_bound -name b6 -effort high {INST_1 INST_2}

report_bounds

get_bounds

get_bound_shapes 

remove_placement_blockages //speccify bound name

===>Voltage Areas

A voltage area is a physical placement area for the cells associated with a power domain. 

For multivoltage designs, the power domains are defined in the UPF specification. For 

single-voltage designs, the tool creates a default power domain when you read the Verilog 

netlist and associates it with a default voltage area, which comprises of the core area of the 

block.

The placer treats a voltage area the same as an exclusive move bound; it must place the 

cells in a voltage area within a specified region and it must place all other cells outside of the 

voltage area. Voltage areas can be rectangular or rectilinear. In addition, they can be 

disjoint, nested, or overlapping. For overlapping voltage areas, the effective shape of each 

voltage area is determined by the stacking order of the voltage area shapes.

===>Density Constraints

Density constraints control how densely cells can be packed. You can control the overall 

placement density for the block or the cell density for specific regions. To control the cell 

density for specific regions, you use partial blockages.

To control how densely cells can be packed, use the place.coarse.max_density

application option. You can set this application option to a value between one and the overall 

average utilization of the block. Choosing a value near one allows cells to clump together 

more densely. A value of one allows no gaps between cells. You should choose a high value 

for blocks with low utilization to improve timing and a low value for congested blocks to avoid 

cell clumping. By default, this application option is set to 0, which disables this feature.

For example, if the utilization of a block is 40 percent, you can choose a value between 0.4 

and 1. 

icc2_shell> set_app_options -name place.coarse.max_density -value 0.6

===>Cell Spacing Constraints

Cell spacing constraints control the spacing between a standard cell and another standard 

cell or a boundary (the chip boundary, a hard macro, a hard macro keepout margin, a hard 

placement blockage, or a voltage area guard band). You assign library cells to groups (the 

boundaries are in a predefined group named SNPS_BOUNDARY), and then define the 

required spacing between cells in these groups.