Phyical deign flow Thank for @VLSI guru
PD flow by maven silicon
SHORT CUTS FOR Fusion Compiler or ICC tool
short key Type Action Name or Function
---------------------------------------------------------------------
+ Menu View->Zoom->Zoom In
- Menu View->Zoom->Zoom Out
0 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal10} -quiet]
1 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal1} -quiet]
2 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal2} -quiet]
3 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal3} -quiet]
4 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal4} -quiet]
5 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal5} -quiet]
6 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal6} -quiet]
7 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal7} -quiet]
8 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal8} -quiet]
9 Tcl gui_set_layout_layer_visibility -toggle [get_layers -filter {mask_name == metal9} -quiet]
= Menu View->Zoom->Zoom In
? Tcl ::menus::query_selection_preview
A Menu View->Zoom->Zoom To Design
C Menu Edit->Copy
D Menu Edit->Delete
E Menu (hidden) View->Next Error
F Menu View->Zoom->Zoom Fit All
G Menu View->Grid->Show Litho Grid
H Menu Search Commands
I Menu View->Zoom->Zoom In
L Menu View->Mouse Tool->Line Selection Mode
M Menu Edit->Move
O Menu View->Zoom->Zoom Out
P Menu View->Mouse Tool->Smart Selection Mode
Q Menu Select->Query Selection
R Menu View->Refresh
S Menu Edit->Stretch
T Menu View->Zoom->Zoom To...
V Menu Edit->Route Utilities->Cycle Via Def Forward
W Menu View->Mouse Tool->Rectangle Selection Mode
X Menu Edit->Cut
Z Menu View->Mouse Tool->Zoom In
Esc Menu (hidden) View->Mouse Tool->ResetTool
Tab Tcl catch {gui_set_mouse_tool_option -tool [gui_mouse_tool -current -window [gui_get_current_window -types Layout]] -option delta -value manual}
Backspace Menu (hidden) View->Mouse Tool->DeletePoint
Del Menu Schematic->Delete
Home Menu (hidden) View->Zoom->Scroll Home Horizontal
End Menu (hidden) View->Zoom->Scroll End Horizontal
Left Menu (hidden) View->Zoom->Scroll Left
Up Menu (hidden) View->Zoom->Scroll Up
Right Menu (hidden) View->Zoom->Scroll Right
Down Menu (hidden) View->Zoom->Scroll Down
PgUp Menu (hidden) View->Zoom->Scroll Up Page
PgDown Menu (hidden) View->Zoom->Scroll Down Page
F1 Menu (hidden) View->Mouse Tool->CycleTool
F2 Tcl ::snpsLayout::visToolBarShowTab 1
F3 Tcl ::snpsLayout::visToolBarShowTab 0
F4 Menu Task->Task Assistant
F6 Tcl ::snpsLayout::visToolBarShowTab 2
F7 Menu View->Toolbars->Console
F8 Menu View->Toolbars->View Settings
F9 Tcl gui_operate_mru_toolbar -window [gui_get_current_window -mru] -command popup -ind 0 -quiet
F10 Menu View->Toolbars->Favorites
Shift+C Menu Create->Via
Shift+D Menu Edit->Delete Disconnected
Shift+E Menu (hidden) View->Previous Error
Shift+F Menu (hidden) View->Toggle Fixed Status of Selected Errors
Shift+H Menu Create->Shape
Shift+I Menu View->InfoTip
Shift+L Menu Edit->Split
Shift+M Menu Edit->Merge Shapes
Shift+P Menu View->Mouse Tool->Pan
Shift+Q Menu View->Toolbars->Query
Shift+R Menu Create->Route
Shift+S Menu Edit->Options...
Shift+U Menu Edit->Quick Connect
Shift+V Menu Edit->Route Utilities->Cycle Via Def Backward
Shift+W Menu Edit->Stretch Connected
Shift+Z Menu View->Zoom->Zoom Out
Shift+F1 Menu (hidden) View->Mouse Tool->CycleBackTool
Ctrl+/ Menu Select->By Name Toolbar
Ctrl+0 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal10} -quiet]
Ctrl+1 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal1} -quiet]
Ctrl+2 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal2} -quiet]
Ctrl+3 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal3} -quiet]
Ctrl+4 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal4} -quiet]
Ctrl+5 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal5} -quiet]
Ctrl+6 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal6} -quiet]
Ctrl+7 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal7} -quiet]
Ctrl+8 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal8} -quiet]
Ctrl+9 Tcl gui_set_layout_layer_visibility -only [get_layers -filter {mask_name == metal9} -quiet]
Ctrl+B Menu Select->By Name...
Ctrl+D Menu Select->Clear
Ctrl+E Menu (hidden) View->Next Error Type
Ctrl+F Menu View->Zoom->Zoom Fit Top
Ctrl+G Menu View->Grid->Cycle grid spacing
Ctrl+H Menu Highlight->Selected
Ctrl+K Menu View->Preferences...
Ctrl+L Menu Select->Selection List
Ctrl+M Menu Highlight->Clear All
Ctrl+N Menu Highlight->Next Color
Ctrl+O Menu File->Open Block...
Ctrl+P Menu View->Mouse Tool->Pan
Ctrl+Q Menu View->Mouse Tool->Query
Ctrl+R Menu Edit->Properties
Ctrl+S Menu File->Save Block...
Ctrl+T Menu View->Zoom->Zoom Fit Selection
Ctrl+U Menu View->Mouse Tool->Ruler
Ctrl+W Menu Window->Close View
Ctrl+Y Menu Edit->Redo
Ctrl+Z Menu Edit->Undo
Ctrl+[ Menu Create->Edit Group
Ctrl+` Menu Window->NextWindow
Ctrl+| Menu View->Flylines->Net Connections
Ctrl+~ Menu Window->PreviousWindow
Ctrl+Tab Menu Window->NextView
Ctrl+Backtab Menu Window->PreviousView
Ctrl+Home Menu (hidden) View->Zoom->Scroll Home Vertical
Ctrl+End Menu (hidden) View->Zoom->Scroll End Vertical
Ctrl+Left Menu (hidden) View->Zoom->Ctrl Scroll Left
Ctrl+Up Menu (hidden) View->Zoom->Ctrl Scroll Up
Ctrl+Right Menu (hidden) View->Zoom->Ctrl Scroll Right
Ctrl+Down Menu (hidden) View->Zoom->Ctrl Scroll Down
Ctrl+F1 Tcl ::menus::query_selection_expand
Ctrl+Shift+A Menu Select->Related Objects->Voltage Areas
Ctrl+Shift+B Menu Select->Related Objects->Bounds
Ctrl+Shift+C Menu Select->Related Objects->Cells
Ctrl+Shift+E Menu View->Error Browser...
Ctrl+Shift+F Menu Highlight->Net Flylines of Selected Objects
Ctrl+Shift+H Menu Highlight->Nets of Selected Objects
Ctrl+Shift+I Menu Select->Related Objects->Input Connections
Ctrl+Shift+M Menu Select->Related Objects->Macros
Ctrl+Shift+N Menu Select->Related Objects->Nets
Ctrl+Shift+O Menu Select->Related Objects->Output Connections
Ctrl+Shift+P Menu Select->Related Objects->Connections
Ctrl+Shift+R Menu Select->Related Objects->Net Routing
Ctrl+Shift+S Menu (hidden) Edit->Snapping
Ctrl+Shift+T Menu Select->Related Objects->Terminals
Ctrl+Shift+V Menu Select->Related Objects->Net Vias
Ctrl+Shift+W Menu Select->Related Objects->Net Shapes
Alt+1 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 1 -quiet
Alt+2 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 2 -quiet
Alt+3 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 3 -quiet
Alt+4 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 4 -quiet
Alt+5 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 5 -quiet
Alt+6 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 6 -quiet
Alt+7 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 7 -quiet
Alt+8 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 8 -quiet
Alt+9 Tcl gui_execute_recent_item -window [gui_get_current_window] -ind 9 -quiet
Alt+G Menu View->Grid->Show User Grid
Alt+R Menu (hidden) ECOhidden->Remove Cells
Alt+Z Menu View->Zoom->Zoom Layout Views to Current View
Alt+Home Menu (hidden) View->Zoom->Scroll Home
Alt+End Menu (hidden) View->Zoom->Scroll End
Ctrl+Alt+E Menu (hidden) View->Previous Error Type
Ctrl+Alt+T Menu View->Zoom->Zoom Fit Highlight
1) What is Clock Skew in VLSI ?
A) As the clock on its way from Source/PLL to Destination/Leaf node , It propagates through the net path or buffers and clock-gates then the clock gets delayed due to the parasitics (R,L,C) of net path or buffer transition and load capacitance and fanout load will be effects ,There by the clock delay difference between Source node to end node is called as Skew of the Clock.
GLOBAL SKEW :- It is the Skew measured in the critical/longest/Max path having maximum delay difference.
LOCAL SKEW:- It is the Skew measured in the short/least/min path having minimum delay difference.
2)What is Floorplanning ?
A) Floorplanning is the process of partitioning logical blocks into physical blocks, sizing and
placing the blocks, performing a floorplan-level placement of macros and standard cells, and
creating a power plan. The goal of floorplanning is to increase the efficiency of downstream
physical design steps to enable a robust, optimized design. To generate accurate budget
estimates for the physical blocks, you generate timing estimates to guide timing budget
allocation between the blocks and top-level cells in the design. Floorplanning can also be an
iterative process that reshapes blocks, creates a new cell placement, reallocates timing
budgets, and rechecks top-level timing until an optimal floorplan is created.
3)What are the types of Floorplan styles in ICC2 tool ?
A) Different floorplan styles to meet the requirements of your design.
• Channeled Floorplans
• Abutted Floorplans
• Narrow-Channel Floorplans
4)How to fix setup and hold violations in reg2reg path ?
A) Before fixing the Setup or Hold Violation you must consider that the timing of the launch path or capture path modifying between this reg2reg must not alter the clock path and data path in next to this or previous to this reg2reg block..
Such that for fixing the Setup , we prefer to reduce combinational data path delay between reg2reg, by inserting buffers to increase the signal strength there by the transition decreases will impact in reducing the cell delay in data path ,Upsizing or Cell swapping from HVT to LVT ,
For Hold fixing it is similarly opposite to setup fixing process, But while fixing hold it should not disturb the setup time margin.
5)What is Synthesis ?
A) Synthesis is the process of generating a technology dependent gate-level netlist for an IC design that has been
defined with a hardware description language (HDL). Synthesis includes reading the
HDL source code and optimizing the design created from that description.
• Optimization is the step in the synthesis process that implements a combination of library
cells that best meet the functional, timing, area, and power requirements of the design.
• Compile is the Design Compiler process that executes the synthesis and optimization
steps. After you read in the design and perform other necessary tasks, you run the{ compile_ultra }or { compile }command to generate a gate-level netlist for the design.
6)What is the tool used for Synthesis?
A) Design Compiler for logic synthesis, which converts a design description written in
a hardware description language, such as Verilog or VHDL, into an optimized gate-level
netlist mapped to a specific logic library. When the synthesized design meets functionality,
timing, power, and other design goals, you can pass the design to the IC Compiler or IC
Compiler II tool for physical implementation of place and routing.
7) What is Design Compiler tool ?
A)Design
Compiler optimizes designs to provide the smallest and fastest logical representation of a
given function or HDL description.
It comprises tools that synthesize your HDL descriptions into optimized,
technology-dependent, gate-level designs.
It supports a wide range of flat and hierarchical
design styles and can optimize both combinational and sequential designs for speed, area,
and power.
8)What are the modes of synthesis performed using Design Compiler ?
A) Design Compiler works in the following modes.
Wire load mode and topographical
mode are tool modes. When you start Design Compiler, you must choose either wire load
mode or topographical mode.
Multimode and UPF mode are not tool modes. Multimode
allows you to operate the tool under multiple operating conditions and multiple modes, such
as test mode and standby mode. UPF mode allows you to specify advanced low-power
methodologies. Multimode and UPF mode are available only in topographical mode.
• Wire Load Mode (Default)
• Topographical Mode
=>Multimode
=> UPF Mode
9)What are the classifications of DRCs ?
A) DRCs are classified as two types , Base DRC and Metal DRC ,
Base DRC are fixed during P&R
Metal DRC are fixed during Sign off stages
10)How do you fix the Setup violations in Placement stage?
A) Path groups are performed to minimize the setup violations in placement stage, By creating the list of Violating end points as a group, Then the tool tries to optimize the Timing paths in pathgroups by which the TNS can be reduced by fixing the setup violations in defined group.
group_path -weight 50 -name LATEARRIVAL -critical_range 10000 -to clk
group_path -name group3 -from in3 -to FF1/D -weight 2.5
The weight argument must be between 0.0 and 100.0; the default is 1.0.
A weight of 0.0 eliminates the paths in this group from cost function calculations. Do not use very small values such as 0.0001.
Smaller values can prevent the tool from implementing small improvements to the design
The range_value argument must be positive or 0.0;
A range of 0.0 means that only the most critical paths are optimized.
If you specify a nonzero
range, other near-critical violating paths within that amount of the worst path are also optimized if possible.
To optimize more than one critical path to an endpoint, use a separate group_path command for each distinct critical path to that
endpoint. To optimize all violating paths, specify a range value that is larger than any expected path violation.
if the critical range is 2.0 ns and the worst violator has a delay of 10.0 ns,
Design Compiler optimizes all paths that have a delay between 8.0 and 10.0 ns.
When the critical range is large enough to include all violators,
the critical negative slack is equal to the total negative slack.
To - If you specify a clock, all registers and primary outputs related to that clock are used as path endpoints. If you specify a cell, one
path endpoint on that cell is affected.
To create path groups before optimization, run the create_auto_path_groups
command after reading the RTL, analyzing and elaborating, and reading the SDC
constraints:
> create_auto_path_groups -mode rtl
> compile_ultra
> remove_auto_path_groups
> report_qor
11)What is a critical path ?
A) The timing path ones with the worst slack violation
12)What is relative placement ?
A) Relative placement is usually applied to data paths and registers, but you can apply it to
any cells in your design, controlling the exact relative placement topology of gate-level
logic groups and defining the circuit layout. You can use relative placement to explore QoR
benefits, such as shorter wire lengths, reduced congestion, better timing, skew control,
fewer vias, better yield, and lower dynamic and leakage power.
create_rp_group Creates new relative placement groups.
add_to_rp_group Adds items to relative placement groups.
set_rp_group_options Sets relative placement group attributes.
report_rp_group_options Reports attributes for relative placement groups.
get_rp_groups Creates a collection of relative placement groups that match
certain criteria.
write_rp_groups Writes out relative placement information for specified groups.
all_rp_groups Returns a collection of specified relative placement groups and
all subgroups in their hierarchy.
all_rp_hierarchicals Returns a collection of hierarchical relative placement groups
that are ancestors of specified groups.
all_rp_inclusions Returns a collection of hierarchical relative placement groups
that include specified groups.
all_rp_instantiations Returns a collection of hierarchical relative placement groups
that instantiate specified groups.
all_rp_references Returns a collection of relative placement groups that contain
specified cells (either leaf cells or hierarchical cells that contain
instantiated relative placement groups).
check_rp_groups Checks relative placement constraints and reports failures.
remove_rp_groups Removes a list of relative placement groups.
remove_rp_group_options Reports attributes for the specified relative placement groups.
remove_from_rp_group Removes an item (cell, relative placement group, or keepout)
from the specified relative placement groups.
rp_group_inclusions Returns collections for directly embedded included groups
(added to a group by using the add_to_rp_group -hierarchy
command) in all or specified groups.
rp_group_instantiations Returns collections for directly embedded instantiated groups
(added to a group by using the add_to_rp_group -hierarchy
-instance command) in all or specified groups.
rp_group_references Returns collections for directly embedded leaf cells (added to
a group by using the add_to_rp_group -leaf command),
directly embedded included cells that contain hierarchically
instantiated cells (added to the included group by using the
add_to_rp_group -hierarchy -instance command), or both
in all or specified relative placement groups.
13) What is Magnet Placement ?
A) Magnet placement improves timing and congestion correlation between Design Compiler
and IC Compiler or IC Compiler II. Magnet placement moves standard cells closer to
objects specified as magnets.
This command used only after the placement of standard cells,
magnet_placement [options] magnet_objects
-cells object_list
Pulls only the cells in the specified object list. You specify only cell objects in the object list. This option is mutually exclusive with -
logical_levels and -stop_by_sequential_cells.
The cells that you specify should form an intact datapath with magnet object. For example, if magnet object connects to cell_a, and
cell_a connects to cell_b, you should specify both cell_a and cell_b. These cells do not have to be a timing path
-logical_levels level
Specifies the number of logical levels to pull. By default, level is 1 and only the first-level cells are pulled. This option is mutually
exclusive with the -cells option.
14)What will be the output of a floorplan ?
A) To save physical constraints in IC Compiler II format, use the write_floorplan -format
icc2 command. The output is a directory that contains files in Tcl and DEF format.
File name Constraints transferred
floorplan.def Die area, rows, tracks, components, pins, vias, special nets, keepout
margins and so on
floorplan.tcl Route guides, placement blockages, bounds, layer routing directions,
voltage areas
rp.tcl Relative placement groups
routing_rule.layer.tcl Routing layer constraints on nets
routing_rule.tcl Nondefault routing rule definitions
routing_rule.net.tcl Routing rules on nets
15) What is the command used to report deign characteristic ?
A) report_physical_constraints
The command reports the following physical constraints:
• Die area
• Placement area
• Utilization
• Aspect ratio
• Rectilinear outline
• Port side
• Port location
• Cell location
• Placement blockage
• Wiring keepouts
• Vias
• Design via masters
• Voltage area
• Site rows
• Bounds
• Preroutes
• User shapes
• Routing tracks
• Keepout margins
16) command to get black boxes in design ?
A) get_cell -hierarchy -filter "design_type== black_box"
17) command to get the list of all the load cells
A) all_fanout -from -to -through -only_cells
18) What is multicycle path, When we use them ?
A) Multicycle paths are Reg to Reg paths which has an exceptional case for setup and hold. For a design with the highest frequency of operation (lowest period of clock), For the design to meet the setup timing for reg1 to reg2 then the data pathdelay + Tcq + Tsu -Tskew should be less than the period of clock between reg1 to reg2. If there comes a situation where the logic depth of data path delay is more than single clock period and which cannot be optimised any more will be treated to consider as Multicycle path for setup and hold between reg1 to reg 2. By this approach the timing violation is fixed with out changing the Clock frequency(Clock period remains same).
set_multicycle_path 2 -setup -from [all_inputs] -to [all_registers -data_pins -edge_triggered]
set_multicycle_path 1 -hold -from [all_inputs] -to [all_registers -data_pins -edge_triggered]
Some data paths have huge adders, multipliers, or they
might have deep levels of logic. Or, they might have a high setup requirement for the capturing device (say, a memory ), or the launching device might have a high
Clk-to-output delay (e.g., a memory). Or, the path might be on a clock which has
very high frequency. In many such cases, it might be difficult for the data to meet
the timing requirements of a single cycle. In such cases, the path might have to be
declared as multi cycle.
19) How the clock skewing is performed ?
A) Positive skewing improves setup timing
Negative skewing improves hold timing
Before performing skew adjustment for fixing setup or hold , Make sure there should be positive extra slack ,ie Usefull skew at the next stage of reg to reg.
20) What is SAIF file and why is it used ?
A) Switching activity interchange format or .saif is an ASIIC type file which contains the toggle rate or switching count of the signals in design used for the analysis of power consumption . saif file can generate from VCD or from simulating the RTL or netlist .
21) What are the types of cross talk delay and how they effect the timing ?
A) Cross talk delay is due to the crosstalk noise generated. There are two type of crosstalk delay based on the switching direction of the signal logic.
>If the direction of agressor net which is highly switch and victim net in same direction then the coupling capacitance between net is high ,this is called Positive crosstalk which improves the transition of the victim net and there by delay of net is reduced ,Which is good for setup
>If the direction of agressor net which is highly switch and victim net in opposite direction then the coupling capacitance between net is low, this is called Negative crosstalk which degrades the transition of the net and there by delay of net is increaed, Which is good for hold.
22)What is Dynamic Voltage Frequency Scaling?
A) It is used to control the power consumption of a Chip. as in architecture-driven voltage scaling (multi voltage design), This DVFS relies on the fact that performance
varies as while power consumption varies, unlike
architecture-driven voltage scaling, DVFS is a dynamic technique—both the clock frequency and power consumption vary during
operation.
This method relies on the fact that a processor do not always have to run
at full speed in order to finish all their tasks. If the processor’s
workload does not require all available CPU performance, then we can
slow down the microprocessor to the lowest available performance level
that meets the current demand.
A power controller uses algorithm to determine
the proper clock frequency and power supply based on load estimate and the logic algorithm pings the power controller the required performance. This algorithm program interface updates a register that is visible to the power controller which is in interface between the system-level load estimate
and the commands to the clock generator and power supply.
23)What does .SDC file contain ?
A)
24)What does the report_timing command returns ?
A)
25)What are the clock tree exceptions ?
A) The tool supports the following type of exceptions for the synthesis of the clock tree.
Sink pins : These pins are the end points of clock tree through which the clock can't propagate . The clock tree considers this pins as the end points needed for skew balancing. and optimising for clock tree latency and drvs
Ignore pins : These pins are
Non- Stop Pin
Exclude Pin
Float Pin
Stop Pin
Don’t Touch Subtree
Don’t Buffer Nets
Don’t Size Cells
26)What is core utilization and cell utilization ?
A) Core Utilization = Macro area + Std cell area + Blockage area / Total core area
Core Utilization
determines the core and
module sizes by total
standard cells –and macros density
Cell Utilization = Std cells area / Core area - Macro area - Blockage area
Cell Utilization
determines the core and
module sizes by standard
cell density.
Block halos do not
influence Core Utilization,
but they *do* influence
Cell Utilization
27)How to get coordinates of the selection region ?
A) gui_set_layout_user_command -apply_cmd puts -input_type rectangle
28)How to validate the FINFET grid ?
A) PnR tool supports a FinFET grid to guide the placement of library cells that
contain FinFET devices. The x- and y-spacing and offset values for the FinFET grid are
specified in the technology file.
use the report_grids -type finfet
To check for placement or boundary violations with respect to the FinFET grid, use the
check_finfet_grid
29)What is Halo and how we define in design ?
A) To define a halo rule to check for legal spacing between an enclosed object and its
enclosing objects, use the set_floorplan_halo_rules command. Use options to specify
object types, object sides, object corners, allowed object rotation, and valid or invalid
spacing ranges and values.
The following example creates a floorplan halo rule named halo_rule_1. The rule specifies
that when a routing blockage encloses a macro, the routing blockage must fully enclose
the macro on all sides and there must be a spacing of 3.0 between the routing blockage
and the library cell.
icc2_shell> set_floorplan_halo_rules -name halo_rule_1 \
-from_object_types routing_blockage -layers METAL2 \
-to_object_types hard_macro -sides all -type outer \
-must_enclose -min 3.0
30) What are the stages of placement in fusion compiler?
A) As the fusion compiler supports physical synthesis flow . It has 7 stages in compile_fusion
1)initial_map : maps the generic cells to library cells and perform logic optimization
2)logic_opto : optimizes timing based on logic only, not considering the physical data.
3)initial_place : places the current design coarse placement
4)initial_drc: optimises the placed design for timing,electrical Drc violations ,area ,power, and routability, Hfns occours here.
5)initial_opto: incremental placement to optimize timing and routability.
6)final_place: further optimizes the placed desing
7)final_opto: legalizes the design placement at the end.
31)What are scenarios in physical design?
A) Static timing analysis will be performed on the multiples scenarios ie,(MCMM)
Scenarios=Operating Mode +PVT corners +Parasitics corners (RC interconnect corners and operating conditions used for parasitic extraction) (RC+PVT)
Modes: 1)Test mode 2)functional mode 3)standby mode
RC : 1)Rmax 2)RCmax 3)Rmin 4)RCmin 5)Cmax 6)Cmin
For SETUP: worst case -->slowest (Max delay in Data path)
PVT : process--> slow
voltage-->low
temperature-->High
For HOLD: best case -->Fastest (Min delay in Data path)
PVT :process-->Fast
voltage -->High
temperature-->low
example: xxxx35p140hvtssg0p72v125c.db
35--> poly pitch
ss--> slow slow
0p72v-->0.72 volts
125c-->temperature
For the timing analysis in a design, the cell delays are dependent on variations of the corners ,for the setup and hold analysis.
32) How are ports placement performed?
A) create_pin_guide -boundary {{}{}} -layers {M8 M10} -name pinguide_1 [get_ports *]
set_block_pin_constraints -self -allowed_layers [get_layers {}]
place_pins "*" -self
report_block_pin_constraints -self
33)What are the pins of latch and flop?
A) latch has three pins d,clk,q and flop has d,sin,Shift,clk
reference books
Introduction to VLSI Physical Design : Sarrafzadeh, M., Wong, C.K.: Amazon.in: Books
Any doughts can be discussed
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